Optimization | Modify Add (Integer) Instruction to use LEA instead. (#1971)
* Optimization | Modify Add Instruction to use LEA instead. Currently, the add instruction requires 4 registers to take place. By using LEA, we can effectively perform the same working using 3 registers, reducing memory spills and improving translation efficiency. * Fix IsSameOperandDestSrc1 Check for Add * Use LEA if Dest != SRC1 * Update IsSameOperandDestSrc1 to account for Cases where Dest and Src1 can be same for add * Fix error in logic * Typo * Add paranthesis for clarity * Compare registers as requested. * Cleanup if statement, use same comparison method as generateCopy * Make change as recommended by gdk * Perform check only when Add calls are made * use ensure sametype for lea, fix else * Update comment * Update version #
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@ -514,13 +514,43 @@ namespace ARMeilleure.CodeGen.X86
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Operand src1 = operation.GetSource(0);
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Operand src1 = operation.GetSource(0);
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Operand src2 = operation.GetSource(1);
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Operand src2 = operation.GetSource(1);
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ValidateBinOp(dest, src1, src2);
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if (dest.Type.IsInteger())
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if (dest.Type.IsInteger())
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{
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{
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// If Destination and Source 1 Operands are the same, perform a standard add as there are no benefits to using LEA.
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if (dest.Kind == src1.Kind && dest.Value == src1.Value)
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{
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ValidateBinOp(dest, src1, src2);
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context.Assembler.Add(dest, src2, dest.Type);
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context.Assembler.Add(dest, src2, dest.Type);
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}
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}
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else if (dest.Type == OperandType.FP32)
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else
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{
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EnsureSameType(dest, src1, src2);
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int offset;
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Operand index;
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if (src2.Kind == OperandKind.Constant)
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{
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offset = src2.AsInt32();
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index = null;
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}
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else
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{
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offset = 0;
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index = src2;
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}
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MemoryOperand memOp = MemoryOp(dest.Type, src1, index, Multiplier.x1, offset);
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context.Assembler.Lea(dest, memOp, dest.Type);
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}
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}
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else
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{
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ValidateBinOp(dest, src1, src2);
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if (dest.Type == OperandType.FP32)
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{
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{
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context.Assembler.Addss(dest, src1, src2);
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context.Assembler.Addss(dest, src1, src2);
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}
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}
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@ -529,6 +559,7 @@ namespace ARMeilleure.CodeGen.X86
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context.Assembler.Addsd(dest, src1, src2);
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context.Assembler.Addsd(dest, src1, src2);
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}
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}
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}
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}
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}
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private static void GenerateBitwiseAnd(CodeGenContext context, Operation operation)
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private static void GenerateBitwiseAnd(CodeGenContext context, Operation operation)
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{
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{
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@ -1273,6 +1273,7 @@ namespace ARMeilleure.CodeGen.X86
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switch (operation.Instruction)
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switch (operation.Instruction)
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{
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{
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case Instruction.Add:
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case Instruction.Add:
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return !HardwareCapabilities.SupportsVexEncoding && !operation.Destination.Type.IsInteger();
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case Instruction.Multiply:
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case Instruction.Multiply:
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case Instruction.Subtract:
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case Instruction.Subtract:
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return !HardwareCapabilities.SupportsVexEncoding || operation.Destination.Type.IsInteger();
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return !HardwareCapabilities.SupportsVexEncoding || operation.Destination.Type.IsInteger();
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@ -22,7 +22,7 @@ namespace ARMeilleure.Translation.PTC
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{
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{
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private const string HeaderMagic = "PTChd";
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private const string HeaderMagic = "PTChd";
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private const int InternalVersion = 1943; //! To be incremented manually for each change to the ARMeilleure project.
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private const int InternalVersion = 1971; //! To be incremented manually for each change to the ARMeilleure project.
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private const string ActualDir = "0";
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private const string ActualDir = "0";
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private const string BackupDir = "1";
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private const string BackupDir = "1";
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