Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192)
* Added some 32 bits instructions: * VBIC * VTST * VSRA * Incremented the PTC * Add tests and fix implementation * Fixed VBIC immediate opcode mapping * Hey hey! * Nit. Co-authored-by: gdkchan <gab.dark.100@gmail.com> Co-authored-by: LDj3SNuD <dvitiello@gmail.com> Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
This commit is contained in:
Valentin PONS
GitHub
parent
9d65de74fc
commit
3af2ce74ec
@ -806,6 +806,8 @@ namespace ARMeilleure.Decoders
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SetA32("111100100x00xxxxxxxx1101xxx0xxxx", InstName.Vadd, InstEmit32.Vadd_V, typeof(OpCode32SimdReg));
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SetA32("1111001x1x<<xxxxxxxx0001x0x0xxxx", InstName.Vaddw, InstEmit32.Vaddw_I, typeof(OpCode32SimdRegWide));
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SetA32("111100100x00xxxxxxxx0001xxx1xxxx", InstName.Vand, InstEmit32.Vand_I, typeof(OpCode32SimdBinary));
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SetA32("111100100x01xxxxxxxx0001xxx1xxxx", InstName.Vbic, InstEmit32.Vbic_I, typeof(OpCode32SimdBinary));
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SetA32("1111001x1x000xxxxxxx<<x10x11xxxx", InstName.Vbic, InstEmit32.Vbic_II, typeof(OpCode32SimdImm));
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SetA32("111100110x11xxxxxxxx0001xxx1xxxx", InstName.Vbif, InstEmit32.Vbif, typeof(OpCode32SimdBinary));
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SetA32("111100110x10xxxxxxxx0001xxx1xxxx", InstName.Vbit, InstEmit32.Vbit, typeof(OpCode32SimdBinary));
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SetA32("111100110x01xxxxxxxx0001xxx1xxxx", InstName.Vbsl, InstEmit32.Vbsl, typeof(OpCode32SimdBinary));
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@ -904,7 +906,7 @@ namespace ARMeilleure.Decoders
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SetA32("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls, InstEmit32.Vnmls_S, typeof(OpCode32SimdRegS));
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SetA32("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul, InstEmit32.Vnmul_S, typeof(OpCode32SimdRegS));
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SetA32("111100100x10xxxxxxxx0001xxx1xxxx", InstName.Vorr, InstEmit32.Vorr_I, typeof(OpCode32SimdBinary));
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SetA32("1111001x1x000xxxxxxx0xx10x01xxxx", InstName.Vorr, InstEmit32.Vorr_II, typeof(OpCode32SimdImm));
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SetA32("1111001x1x000xxxxxxx<<x10x01xxxx", InstName.Vorr, InstEmit32.Vorr_II, typeof(OpCode32SimdImm));
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SetA32("111100100x<<xxxxxxxx1011x0x1xxxx", InstName.Vpadd, InstEmit32.Vpadd_I, typeof(OpCode32SimdReg));
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SetA32("111100110x00xxxxxxxx1101x0x0xxxx", InstName.Vpadd, InstEmit32.Vpadd_V, typeof(OpCode32SimdReg));
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SetA32("1111001x0x<<xxxxxxxx1010x0x0xxxx", InstName.Vpmax, InstEmit32.Vpmax_I, typeof(OpCode32SimdReg));
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@ -927,6 +929,7 @@ namespace ARMeilleure.Decoders
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SetA32("1111001x1x>>>xxxxxxx0000>xx1xxxx", InstName.Vshr, InstEmit32.Vshr, typeof(OpCode32SimdShImm));
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SetA32("111100101x>>>xxxxxxx100000x1xxx0", InstName.Vshrn, InstEmit32.Vshrn, typeof(OpCode32SimdShImmNarrow));
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SetA32("<<<<11101x110001xxxx101x11x0xxxx", InstName.Vsqrt, InstEmit32.Vsqrt_S, typeof(OpCode32SimdS));
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SetA32("1111001x1x>>>xxxxxxx0001>xx1xxxx", InstName.Vsra, InstEmit32.Vsra, typeof(OpCode32SimdShImm));
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SetA32("111101001x00xxxxxxxx<<00xxxxxxxx", InstName.Vst1, InstEmit32.Vst1, typeof(OpCode32SimdMemSingle));
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SetA32("111101000x00xxxxxxxx0111xxxxxxxx", InstName.Vst1, InstEmit32.Vst1, typeof(OpCode32SimdMemPair)); // Regs = 1.
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SetA32("111101000x00xxxxxxxx1010xxxxxxxx", InstName.Vst1, InstEmit32.Vst1, typeof(OpCode32SimdMemPair)); // Regs = 2.
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@ -952,6 +955,7 @@ namespace ARMeilleure.Decoders
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SetA32("1111001x1x<<xxxxxxxx0011x0x0xxxx", InstName.Vsubw, InstEmit32.Vsubw_I, typeof(OpCode32SimdRegWide));
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SetA32("111100111x11xxxxxxxx10xxxxx0xxxx", InstName.Vtbl, InstEmit32.Vtbl, typeof(OpCode32SimdTbl));
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SetA32("111100111x11<<10xxxx00001xx0xxxx", InstName.Vtrn, InstEmit32.Vtrn, typeof(OpCode32SimdCmpZ));
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SetA32("111100100x<<xxxxxxxx1000xxx1xxxx", InstName.Vtst, InstEmit32.Vtst, typeof(OpCode32SimdReg));
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SetA32("111100111x11<<10xxxx00010xx0xxxx", InstName.Vuzp, InstEmit32.Vuzp, typeof(OpCode32SimdCmpZ));
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SetA32("111100111x11<<10xxxx00011xx0xxxx", InstName.Vzip, InstEmit32.Vzip, typeof(OpCode32SimdCmpZ));
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#endregion
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@ -1,4 +1,4 @@
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using ARMeilleure.Decoders;
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using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System;
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@ -305,6 +305,35 @@ namespace ARMeilleure.Instructions
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorImmBinaryQdQmOpZx32(ArmEmitterContext context, Func2I emit)
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{
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EmitVectorImmBinaryQdQmOpI32(context, emit, false);
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}
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public static void EmitVectorImmBinaryQdQmOpSx32(ArmEmitterContext context, Func2I emit)
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{
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EmitVectorImmBinaryQdQmOpI32(context, emit, true);
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}
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public static void EmitVectorImmBinaryQdQmOpI32(ArmEmitterContext context, Func2I emit, bool signed)
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{
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OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
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Operand res = GetVecA32(op.Qd);
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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Operand de = EmitVectorExtract32(context, op.Qd, op.Id + index, op.Size, signed);
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Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed);
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res = EmitVectorInsert(context, res, emit(de, me), op.Id + index, op.Size);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorTernaryLongOpI32(ArmEmitterContext context, Func3I emit, bool signed)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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@ -15,7 +15,7 @@ namespace ARMeilleure.Instructions
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{
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if (Optimizations.UseSse2)
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{
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EmitVectorBinaryOpF32(context, Intrinsic.X86Pand, Intrinsic.X86Pand);
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EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.X86Pand, n, m));
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}
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else
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{
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@ -23,6 +23,54 @@ namespace ARMeilleure.Instructions
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}
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}
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public static void Vbic_I(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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{
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EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.X86Pandn, m, n));
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}
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else
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{
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EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseAnd(op1, context.BitwiseNot(op2)));
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}
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}
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public static void Vbic_II(ArmEmitterContext context)
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{
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OpCode32SimdImm op = (OpCode32SimdImm)context.CurrOp;
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long immediate = op.Immediate;
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// Replicate fields to fill the 64-bits, if size is < 64-bits.
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switch (op.Size)
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{
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case 0: immediate *= 0x0101010101010101L; break;
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case 1: immediate *= 0x0001000100010001L; break;
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case 2: immediate *= 0x0000000100000001L; break;
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}
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Operand imm = Const(immediate);
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Operand res = GetVecA32(op.Qd);
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if (op.Q)
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{
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for (int elem = 0; elem < 2; elem++)
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{
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Operand de = EmitVectorExtractZx(context, op.Qd, elem, 3);
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res = EmitVectorInsert(context, res, context.BitwiseAnd(de, context.BitwiseNot(imm)), elem, 3);
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}
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}
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else
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{
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Operand de = EmitVectorExtractZx(context, op.Qd, op.Vd & 1, 3);
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res = EmitVectorInsert(context, res, context.BitwiseAnd(de, context.BitwiseNot(imm)), op.Vd & 1, 3);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void Vbif(ArmEmitterContext context)
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{
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EmitBifBit(context, true);
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@ -59,7 +107,7 @@ namespace ARMeilleure.Instructions
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{
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if (Optimizations.UseSse2)
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{
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EmitVectorBinaryOpF32(context, Intrinsic.X86Pxor, Intrinsic.X86Pxor);
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EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.X86Pxor, n, m));
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}
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else
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{
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@ -71,7 +119,7 @@ namespace ARMeilleure.Instructions
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{
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if (Optimizations.UseSse2)
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{
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EmitVectorBinaryOpF32(context, Intrinsic.X86Por, Intrinsic.X86Por);
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EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.X86Por, n, m));
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}
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else
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{
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@ -115,6 +163,15 @@ namespace ARMeilleure.Instructions
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void Vtst(ArmEmitterContext context)
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{
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EmitVectorBinaryOpZx32(context, (op1, op2) =>
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{
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Operand isZero = context.ICompareEqual(context.BitwiseAnd(op1, op2), Const(0));
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return context.ConditionalSelect(isZero, Const(0), Const(-1));
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});
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}
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private static void EmitBifBit(ArmEmitterContext context, bool notRm)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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@ -129,6 +129,27 @@ namespace ARMeilleure.Instructions
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EmitVectorUnaryNarrowOp32(context, (op1) => context.ShiftRightUI(op1, Const(shift)));
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}
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public static void Vsra(ArmEmitterContext context)
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{
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OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
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int shift = GetImmShr(op);
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int maxShift = (8 << op.Size) - 1;
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if (op.U)
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{
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EmitVectorImmBinaryQdQmOpZx32(context, (op1, op2) =>
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{
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Operand shiftRes = shift > maxShift ? Const(op2.Type, 0) : context.ShiftRightUI(op2, Const(shift));
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return context.Add(op1, shiftRes);
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});
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}
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else
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{
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EmitVectorImmBinaryQdQmOpSx32(context, (op1, op2) => context.Add(op1, context.ShiftRightSI(op2, Const(Math.Min(maxShift, shift)))));
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}
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}
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private static Operand EmitShlRegOp(ArmEmitterContext context, Operand op, Operand shiftLsB, int size, bool unsigned)
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{
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if (shiftLsB.Type == OperandType.I64)
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@ -547,6 +547,7 @@ namespace ARMeilleure.Instructions
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Vadd,
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Vaddw,
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Vand,
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Vbic,
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Vbif,
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Vbit,
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Vbsl,
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@ -611,10 +612,12 @@ namespace ARMeilleure.Instructions
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Vrecps,
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Vrsqrte,
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Vrsqrts,
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Vsra,
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Vsub,
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Vsubw,
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Vtbl,
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Vtrn,
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Vtst,
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Vuzp,
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Vzip,
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}
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@ -441,6 +441,11 @@ namespace ARMeilleure.Translation
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return Add(Instruction.VectorInsert8, Local(OperandType.V128), vector, value, Const(index));
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}
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public Operand VectorOne()
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{
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return Add(Instruction.VectorOne, Local(OperandType.V128));
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}
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public Operand VectorZero()
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{
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return Add(Instruction.VectorZero, Local(OperandType.V128));
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@ -20,7 +20,7 @@ namespace ARMeilleure.Translation.PTC
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{
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private const string HeaderMagic = "PTChd";
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private const int InternalVersion = 12; //! To be incremented manually for each change to the ARMeilleure project.
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private const int InternalVersion = 13; //! To be incremented manually for each change to the ARMeilleure project.
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private const string BaseDir = "Ryujinx";
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@ -11,11 +11,22 @@ namespace Ryujinx.Tests.Cpu
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{
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#if SimdLogical32
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#region "ValueSource (Types)"
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private static ulong[] _8B4H2S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _Vbif_Vbit_Vbsl_Vand_Vorr_Veor_()
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private static uint[] _Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I_()
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{
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return new uint[]
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{
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0xf2100110u, // VBIC D0, D0, D0
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0xf3300110u, // VBIF D0, D0, D0
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0xf3200110u, // VBIT D0, D0, D0
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0xf3100110u, // VBSL D0, D0, D0
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@ -24,68 +35,121 @@ namespace Ryujinx.Tests.Cpu
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0xf3000110u // VEOR D0, D0, D0
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};
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}
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private static uint[] _Vbic_Vorr_II_()
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{
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return new uint[]
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{
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0xf2800130u, // VBIC.I32 D0, #0 (A1)
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0xf2800930u, // VBIC.I16 D0, #0 (A2)
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0xf2800110u, // VORR.I32 D0, #0 (A1)
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0xf2800910u // VORR.I16 D0, #0 (A2)
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};
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}
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#endregion
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private const int RndCnt = 2;
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[Test, Pairwise]
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public void Vbif_Vbit_Vbsl_Vand_Vorr_Veor([ValueSource("_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_")] uint opcode,
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[Range(0u, 4u)] uint rd,
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[Range(0u, 4u)] uint rn,
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[Range(0u, 4u)] uint rm,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b,
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[Values] bool q)
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public void Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I([ValueSource("_Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I_")] uint opcode,
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[Range(0u, 5u)] uint rd,
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[Range(0u, 5u)] uint rn,
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[Range(0u, 5u)] uint rm,
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[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong z,
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[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong a,
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[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong b,
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[Values] bool q)
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{
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if (q)
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{
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opcode |= 1 << 6;
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rm <<= 1;
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rn <<= 1;
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rd <<= 1;
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rd >>= 1; rd <<= 1;
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rn >>= 1; rn <<= 1;
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rm >>= 1; rm <<= 1;
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}
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, z);
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V128 v2 = MakeVectorE0E1(b, z);
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V128 v0 = MakeVectorE0E1(z, ~z);
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V128 v1 = MakeVectorE0E1(a, ~a);
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V128 v2 = MakeVectorE0E1(b, ~b);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VORR.I32 <Vd>, #<imm>")]
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public void Vorr_II([Range(0u, 4u)] uint rd,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] byte imm,
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[Values(0u, 1u, 2u, 3u)] uint cMode,
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[Values] bool q)
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[Test, Pairwise]
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public void Vbic_Vorr_II([ValueSource("_Vbic_Vorr_II_")] uint opcode,
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[Values(0u, 1u)] uint rd,
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[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong z,
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[Values(byte.MinValue, byte.MaxValue)] [Random(RndCnt)] byte imm,
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[Values(0u, 1u, 2u, 3u)] uint cMode,
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[Values] bool q)
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{
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uint opcode = 0xf2800110u; // VORR.I32 D0, #0
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if ((opcode & 0x800) != 0) // cmode<3> == '1' (A2)
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{
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cMode &= 1;
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}
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if (q)
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{
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opcode |= 1 << 6;
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rd <<= 1;
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rd >>= 1; rd <<= 1;
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}
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opcode |= (uint)(imm & 0xf) << 0;
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opcode |= (uint)(imm & 0x70) << 12;
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opcode |= (uint)(imm & 0x80) << 17;
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opcode |= ((uint)imm & 0xf) << 0;
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opcode |= ((uint)imm & 0x70) << 12;
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opcode |= ((uint)imm & 0x80) << 17;
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opcode |= (cMode & 0x3) << 9;
|
||||
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
|
||||
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v0 = MakeVectorE0E1(z, ~z);
|
||||
|
||||
SingleOpcode(opcode, v0: v0);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("VTST.<dt> <Vd>, <Vn>, <Vm>")]
|
||||
public void Vtst([Range(0u, 5u)] uint rd,
|
||||
[Range(0u, 5u)] uint rn,
|
||||
[Range(0u, 5u)] uint rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong a,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong b,
|
||||
[Values(0u, 1u, 2u)] uint size,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint opcode = 0xf2000810u; // VTST.8 D0, D0, D0
|
||||
|
||||
if (q)
|
||||
{
|
||||
opcode |= 1 << 6;
|
||||
|
||||
rd >>= 1; rd <<= 1;
|
||||
rn >>= 1; rn <<= 1;
|
||||
rm >>= 1; rm <<= 1;
|
||||
}
|
||||
|
||||
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
|
||||
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
|
||||
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
|
||||
|
||||
opcode |= (size & 0x3) << 20;
|
||||
|
||||
V128 v0 = MakeVectorE0E1(z, ~z);
|
||||
V128 v1 = MakeVectorE0E1(a, ~a);
|
||||
V128 v2 = MakeVectorE0E1(b, ~b);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
@ -28,7 +28,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
0xf3000d00u, // VPADD.F32 D0, D0, D0
|
||||
0xf3000f00u, // VPMAX.F32 D0, D0, D0
|
||||
0xf3200f00u // VPMIN.F32 D0, D0, D0
|
||||
0xf3200f00u // VPMIN.F32 D0, D0, D0
|
||||
};
|
||||
}
|
||||
|
||||
@ -41,7 +41,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
VpaddI8,
|
||||
0xf2000a00u, // VPMAX.S8 D0, D0, D0
|
||||
0xf2000a10u // VPMIN.S8 D0, D0, D0
|
||||
0xf2000a10u // VPMIN.S8 D0, D0, D0
|
||||
};
|
||||
}
|
||||
#endregion
|
||||
@ -189,7 +189,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
[Explicit]
|
||||
[Test, Pairwise, Description("VADD.f32 V0, V0, V0")]
|
||||
public void Vadd_f32([Values(0u)] uint rd,
|
||||
public void Vadd_f32([Values(0u)] uint rd,
|
||||
[Values(0u, 1u)] uint rn,
|
||||
[Values(0u, 2u)] uint rm,
|
||||
[ValueSource("_2S_F_")] ulong z0,
|
||||
|
||||
@ -9,50 +9,162 @@ namespace Ryujinx.Tests.Cpu
|
||||
public sealed class CpuTestSimdShImm32 : CpuTest32
|
||||
{
|
||||
#if SimdShImm32
|
||||
|
||||
#region "ValueSource (Types)"
|
||||
private static ulong[] _1D_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _2S_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _4H_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _8B_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _Vshr_Imm_SU8_()
|
||||
{
|
||||
return new uint[]
|
||||
{
|
||||
0xf2880110u, // VSRA.S8 D0, D0, #8
|
||||
0xf2880210u, // VRSHR.S8 D0, D0, #8
|
||||
0xf2880010u // VSHR.S8 D0, D0, #8
|
||||
};
|
||||
}
|
||||
|
||||
private static uint[] _Vshr_Imm_SU16_()
|
||||
{
|
||||
return new uint[]
|
||||
{
|
||||
0xf2900110u, // VSRA.S16 D0, D0, #16
|
||||
0xf2900210u, // VRSHR.S16 D0, D0, #16
|
||||
0xf2900010u // VSHR.S16 D0, D0, #16
|
||||
};
|
||||
}
|
||||
|
||||
private static uint[] _Vshr_Imm_SU32_()
|
||||
{
|
||||
return new uint[]
|
||||
{
|
||||
0xf2a00110u, // VSRA.S32 D0, D0, #32
|
||||
0xf2a00210u, // VRSHR.S32 D0, D0, #32
|
||||
0xf2a00010u // VSHR.S32 D0, D0, #32
|
||||
};
|
||||
}
|
||||
|
||||
private static uint[] _Vshr_Imm_SU64_()
|
||||
{
|
||||
return new uint[]
|
||||
{
|
||||
0xf2800190u, // VSRA.S64 D0, D0, #64
|
||||
0xf2800290u, // VRSHR.S64 D0, D0, #64
|
||||
0xf2800090u // VSHR.S64 D0, D0, #64
|
||||
};
|
||||
}
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntShiftImm = 2;
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vrshr_Vshr_Imm([Values(0u)] uint rd,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[Values(0u, 1u, 2u, 3u)] uint size,
|
||||
[Random(RndCnt), Values(0u)] uint shiftImm,
|
||||
[Random(RndCnt)] ulong z,
|
||||
[Random(RndCnt)] ulong a,
|
||||
[Random(RndCnt)] ulong b,
|
||||
[Values] bool u,
|
||||
[Values] bool q,
|
||||
[Values] bool round)
|
||||
public void Vshr_Imm_SU8([ValueSource("_Vshr_Imm_SU8_")] uint opcode,
|
||||
[Range(0u, 3u)] uint rd,
|
||||
[Range(0u, 3u)] uint rm,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong b,
|
||||
[Values(1u, 8u)] [Random(2u, 7u, RndCntShiftImm)] uint shiftImm,
|
||||
[Values] bool u,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint opcode = 0xf2800010u; // VMOV.I32 D0, #0 (immediate value changes it into SHR)
|
||||
if (q)
|
||||
{
|
||||
opcode |= 1 << 6;
|
||||
rm <<= 1;
|
||||
rd <<= 1;
|
||||
}
|
||||
uint imm6 = 16 - shiftImm;
|
||||
|
||||
if (round)
|
||||
{
|
||||
opcode |= 1 << 9; // Turn into VRSHR
|
||||
}
|
||||
Vshr_Imm_SU(opcode, rd, rm, z, b, imm6, u, q);
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vshr_Imm_SU16([ValueSource("_Vshr_Imm_SU16_")] uint opcode,
|
||||
[Range(0u, 3u)] uint rd,
|
||||
[Range(0u, 3u)] uint rm,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong b,
|
||||
[Values(1u, 16u)] [Random(2u, 15u, RndCntShiftImm)] uint shiftImm,
|
||||
[Values] bool u,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint imm6 = 32 - shiftImm;
|
||||
|
||||
Vshr_Imm_SU(opcode, rd, rm, z, b, imm6, u, q);
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vshr_Imm_SU32([ValueSource("_Vshr_Imm_SU32_")] uint opcode,
|
||||
[Range(0u, 3u)] uint rd,
|
||||
[Range(0u, 3u)] uint rm,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong b,
|
||||
[Values(1u, 32u)] [Random(2u, 31u, RndCntShiftImm)] uint shiftImm,
|
||||
[Values] bool u,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint imm6 = 64 - shiftImm;
|
||||
|
||||
Vshr_Imm_SU(opcode, rd, rm, z, b, imm6, u, q);
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vshr_Imm_SU64([ValueSource("_Vshr_Imm_SU64_")] uint opcode,
|
||||
[Range(0u, 3u)] uint rd,
|
||||
[Range(0u, 3u)] uint rm,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong b,
|
||||
[Values(1u, 64u)] [Random(2u, 63u, RndCntShiftImm)] uint shiftImm,
|
||||
[Values] bool u,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint imm6 = 64 - shiftImm;
|
||||
|
||||
Vshr_Imm_SU(opcode, rd, rm, z, b, imm6, u, q);
|
||||
}
|
||||
|
||||
private void Vshr_Imm_SU(uint opcode, uint rd, uint rm, ulong z, ulong b, uint imm6, bool u, bool q)
|
||||
{
|
||||
if (u)
|
||||
{
|
||||
opcode |= 1 << 24;
|
||||
}
|
||||
|
||||
uint imm = 1u << ((int)size + 3);
|
||||
imm |= shiftImm & (imm - 1);
|
||||
if (q)
|
||||
{
|
||||
opcode |= 1 << 6;
|
||||
|
||||
rd >>= 1; rd <<= 1;
|
||||
rm >>= 1; rm <<= 1;
|
||||
}
|
||||
|
||||
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
|
||||
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
|
||||
opcode |= ((imm & 0x3f) << 16) | ((imm & 0x40) << 1);
|
||||
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
|
||||
|
||||
V128 v0 = MakeVectorE0E1(z, z);
|
||||
V128 v1 = MakeVectorE0E1(a, z);
|
||||
V128 v2 = MakeVectorE0E1(b, z);
|
||||
opcode |= (imm6 & 0x3f) << 16;
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
|
||||
V128 v0 = MakeVectorE0E1(z, ~z);
|
||||
V128 v1 = MakeVectorE0E1(b, ~b);
|
||||
|
||||
SingleOpcode(opcode, v0: v0, v1: v1);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user